The present invention relates to semiconductor integrated circuit devices, and more particularly to a technique of adjusting impedance of signal transmission wirings for superhigh speed devices.
For a superhigh speed device such as GaAs (gallium arsenide) IC operating with frequencies in a GHz band, it is necessary to adjust the input impedance to the characteristic impedance of the signal transmission line thereof. This adjustment is required because there is a possibility that circuit malfunctions due to signal reflection and waveform distortion would result if the above-mentioned high impedances are not matched in transmitting high frequency signals. There is also a possibility that circuit malfunctions due to signal reflection and waveform distortion would result if the characteristic impedance of the signal transmission line mentioned above is not matched to the impedance at its terminal. For these reasons, in an IC package in which a superhigh speed device is mounted for example, the value of the characteristic impedance of the package wiring is made to match that of the impedance of the signal source and at the same time, the impedance of the signal transmission line in the package is adjusted by arranging a load resistance for adjusting the impedance at the terminal of the package wiring.
FIG. 11 through FIG. 13 are views showing the specific examples of the above-mentioned terminal resistance. In these figures, a semiconductor chip 21 is mounted in the cavity of an IC package 20 made of ceramics, and on the outer circumference of a substrate 22, a package wiring 23 is formed. A plurality of the above-mentioned package wirings 23 are mounted along the outer circumference of the substrate 22. (By outer circumference it is meant to include an outer area of the package substrate 22 which surrounds the cavity of the IC package, the cavity corresponding to a central area of the package. In these figures, however, only one of the wirings is shown for convenience' sake. The semiconductor chip 21 and the package wiring 23 are connected through a bonding wire 24, and an outer lead 25 is brazed to the other end of the package wiring 23. FIG. 11 is a view showing an example of a structure in which the terminal resistance is produced by a chip resistance 26 mounted in the cavity. One end of the above-mentioned chip resistance 26 is connected to the package wiring 23 through the bonding wire 24 while the other end thereof is connected to the grounding potential (GND) through the bonding wire 24. On the other hand, FIG. 12 is a view showing an example of a structure in which the terminal resistance is produced by a resistance element 27 in the semiconductor chip 21. Also, FIG. 13 is a view showing an example of a structure in which the terminal resistance is produced by a thick film resistance 28 formed on the substrate 22. In this respect, there is, for example, an article regarding a technique for adjusting impedance of the IC package for superhigh speed devices in "Nikkei Microdevices" pp.111 to 117 published in Nov. , 1985 by Nikkei-McGraw Hill Inc. Also, there are, for example, disclosures regarding the IC package in which a load resistance is mounted for adjusting impedance at the terminal of the package wiring in Japanese Patent Laid-Open No. 176153/1987, Japanese Patent Laid-Open No. 107129/1988, Japanese Patent Laid-Open No. 256001/1988, Japanese Patent Laid-Open No. 256002/1988, Japanese Patent Laid-Open No. 258046/1988, etc.